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Corresponding Author

Zeng-Lin Wang(wangzl@snnu.edu.cn)

Abstract

With the continuous improvement of semiconductor integration, the resistivity of copper interconnect lines increases rapidly. When the width of the interconnect line is close to 7 nm, the resistivity of copper becomes the same as that of cobalt. International Business Machines Corporation (IBM) and Advanced Semiconductor Incorporation (ASI) have used cobalt to replace copper as a next-generation interconnect material. However, the fabrication of the cobalt seed layer and the super filling of electroplating cobalt for the 7 nm via-holes have been still the large challenge. Electroless plating is a very simple method to form a seed layer on the surface of an insulator. By the bottom-up filling of electroless plating, via-holes with several nanometers could be filled completely. In this paper, the research progress in electroless cobalt plating is reviewed, and the effects of the reductant species on the deposition rate and the film quality of electroless cobalt plating are analyzed. Meanwhile, based on long-term and a lot of studies, a bottom-up filling of electroless cobalt plating for 7 nm via-hole in semiconductor cobalt interconnects is proposed.

Graphical Abstract

Keywords

electroless cobalt plating, bottom-up filing, electroless copper plating, super electroless cobalt plating, copper interconnects, cobalt interconnects

Publication Date

2022-07-28

Online Available Date

2022-05-20

Revised Date

2022-05-07

Received Date

2022-04-02

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