Research Progress of Copper Electrodeposition Filling Mechanism in Silicon Vias

Authors

Yun-Na Sun, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;2. School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China;Follow
Yong-Jin Wu, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;2. School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China;
Dong-Dong Xie, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;2. School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China;
Han Cai, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;2. School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai 200240, China;
Yan Wang, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;
Gui-Fu Ding, 1. National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Shanghai Jiao Tong University, Shanghai 200240, China;Follow

Corresponding Author

Yun-Na Sun(Cecilia_Sun@sjtu.cn);
Gui-Fu Ding(gfding@sjtu.edu.cn)

Abstract

Aiming at the electroplating filling problem of deep via TSV (through silicon via) interconnection, the multi-compatible integrated manufacturing technology team at the Shanghai Jiao Tong University has completed the numerical solution of the equations and realized the numerical simulation of TSV filling mode by applying the finite element method with arbitrary Lagrange Euler algorithm. The filling mechanisms of blind vias, the butterfly filling form for the through vias and the simultaneous filling mode of vias with different aspect ratios are analyzed by simulation, contributing to the parameter optimization and sample manufacturing. The effects of electroplating current density and heat treatment temperature on the mechanical properties of electroplating filled TSV-Cu were investigated by in-situ compression test and uniaxial film tensile test. With the increase of heat treatment temperature, the fracture strength and yield strength decreased significantly, and the Young's modulus changed slowly in a corrugated shape. The influence of the current density was more complexed. Based on the above research results, the thermal deformation mechanism of interconnection structure caused by thermal mismatch stress was studied through the self-built in-situ testing system, which gives change in the real-time deformation of TSV-Cu with temperature. The results showed that the thermal deformation process can be divided into the elastic deformation stage, the quasi plastic strengthening stage and the plastic deformation stage.

Graphical Abstract

Keywords

through silicon via, numerical simulation, Cu electrodeposition mechanism, arbitrary lagrange-eulerian, 2.5-dimension interposer

DOI Link

https://doi.org/10.13208/j.electrochem.2213001

Publication Date

2022-07-28

Online Available Date

2022-04-16

Revised Date

2022-03-28

Received Date

2022-02-18

Recommended Citation

Yun-Na Sun, Yong-Jin Wu, Dong-Dong Xie, Han Cai, Yan Wang, Gui-Fu Ding. Research Progress of Copper Electrodeposition Filling Mechanism in Silicon Vias[J]. Journal of Electrochemistry, 2022 , 28(7): 2213001.
DOI: 10.13208/j.electrochem.2213001
Available at: https://jelectrochem.xmu.edu.cn/journal/vol28/iss7/10